Arm at Exascale: Inside the New Number One Supercomputer

The 67th TOP500 list, announced at ISC 2026 in Hamburg, delivered a major shakeup to the high-performance computing world. For the first time in nine years, a Chinese system has been submitted to the list, and it immediately claimed the number one spot. The LineShine supercomputer, located in Shenzhen, China, did not achieve this feat by stacking the latest power-hungry GPUs. Instead, it is a massive, CPU-only system built on the Arm architecture.

This development challenges the prevailing industry narrative that GPUs are the only viable path to exascale performance. While the hyperscale cloud and AI sectors are locked in an arms race to build massive GPU clusters for low-precision matrix math, LineShine proves that a highly optimized, CPU-centric architecture can dominate traditional double-precision (FP64) scientific computing. It also highlights a widening architectural split between traditional High-Performance Computing (HPC) and modern AI-training infrastructures.

The Architecture of the LX2 Core

At the heart of the LineShine system is the LX2, an Armv9-compliant processor designed specifically for highly parallel vector workloads. The chip features native support for Scalable Vector Extension 2 (SVE2) and Scalable Matrix Extension (SME), which are critical for accelerating mathematical operations without relying on external accelerators.

The physical layout of the LX2 is a study in yield management and modular design. Each processor package is built from two compute dies. Each die contains four clusters of 40 cores. To maximize manufacturing yields, two cores are disabled per cluster, leaving 38 active cores. This results in 152 active cores per die, or a massive 304 active cores per physical LX2 package.

The memory and cache hierarchy is engineered to feed this massive core count. Each core has 32 KB of L1 instruction cache and 32 KB of L1 data cache. Each 38-core cluster shares 28.5 MB of L2 cache, yielding 114 MB of L2 per die and a total of 228 MB of L2 cache per package. Running at a modest clock speed of 1.55 GHz, a single LX2 CPU delivers 60.3 TFLOP/s of FP64 compute while drawing 690 watts.

To prevent these 304 cores from starving for data, the package integrates eight stacks of high-bandwidth memory (4 GB per stack, totaling 32 GB per package) that deliver 4 TB/s of bandwidth. While described in terms similar to standard High Bandwidth Memory (HBM), this is likely an indigenous Chinese memory technology. Because 32 GB is relatively small for a processor of this scale, each LX2 is paired with 256 GB of standard DDR5 memory, which acts as a larger, high-capacity spillover tier.

Scaling to 13 Million Cores

Building an exascale system out of these processors requires an incredibly dense packaging and networking strategy.

• Node Level: Each compute node contains two LX2 CPUs. Each CPU is allocated 800 Gbps of networking bandwidth, providing a combined 1.6 Tbps of networking per node.
• Blade Level: Eight of these dual-socket nodes are packed into a single compute blade.
• Frame Level: Sixteen compute blades are combined into a compute frame.
• Cabinet Level: Two frames make up a single compute cabinet.

With 90 compute cabinets in total, the complete LineShine system scales to over 22,000 nodes, housing more than 13 million active CPU cores.

This massive footprint translates to 2.198 Exaflops of sustained FP64 performance (Rmax) out of a theoretical peak of 2.735 Exaflops (Rpeak). During its record-breaking run, the system drew 42.22 Megawatts of power. This yields an FP64 efficiency of 52.07 Gigaflops per Watt. While this efficiency figure lags behind the Green500 leader (which sits at 73.282 Gigaflops per Watt and saw no changes to its top ten list this cycle), it is an exceptional result for a CPU-only architecture.

Importantly, LineShine is not a "LINPACK-special" designed solely to win rankings. On the High-Performance Conjugate Gradient (HPCG) benchmark, which mimics real-world scientific workloads by stressing memory bandwidth and latency rather than raw compute, LineShine achieved 22.004 Petaflops/s. This comfortably beat El Capitan's 17.406 Petaflops/s, proving that the system's memory hierarchy and interconnect can handle highly irregular, communication-heavy codes.

The Developer Angle: Coding for Tiered Memory and Vector Extensions

For software engineers working on high-performance codebases, LineShine is a clear signal of where the hardware frontier is heading. It demands a shift in how we write and optimize parallel software.

First, developers targeting modern Arm-based supercomputers must move beyond fixed-width NEON vector instructions and fully embrace SVE2. SVE2 uses Vector-Length Agnostic (VLA) programming. This means your compiled binary does not hardcode the vector register width (whether it is 128, 256, or 512 bits). Instead, the hardware determines the vector length at runtime. Writing clean, auto-vectorizable C/C++ or Fortran code, or using compiler hints, is necessary to let the compiler use these wide vector pipelines.

Second, the LX2's memory architecture introduces a strict tiered-memory programming model. With only 32 GB of ultra-fast on-package memory and 256 GB of slower DDR5, developers cannot treat memory as a single flat address space. Critical data structures, such as active stencil grids in climate simulations or frequently accessed sparse matrices, must be explicitly pinned to the high-bandwidth memory tier. This requires using tools like custom runtime allocators or operating system NUMA policies to manage memory placement.

Finally, scaling to 13 million cores requires extreme care with message-passing interface (MPI) code. At this scale, collective communication operations like MPI_Allreduce can easily become bottlenecks. Developers must design their algorithms to overlap communication with computation, utilizing non-blocking collectives and topology-aware MPI runtimes to minimize network congestion across the 1.6 Tbps node interconnects.

The Deepening Split Between HPC and AI

The arrival of LineShine, alongside other notable entries like Eni's HPC7 in Italy (a scaled-down version of El Capitan using AMD Instinct MI300A APUs that hit 571.5 Petaflops), highlights a growing divergence in the hardware world.

We are seeing a clear split between traditional scientific supercomputers and massive AI-training clusters. AI giants are building gargantuan systems, such as xAI's Colossus 2, which reportedly houses over 550,000 GPUs. Yet, these systems are conspicuously absent from the TOP500 list.

The reason is simple: their workloads and hardware are optimized for entirely different mathematical regimes. AI training does not require double-precision FP64 math; it thrives on low-precision FP16, BF16, and FP8 matrix operations. A GPU cluster optimized for massive FP8 throughput would perform poorly on a double-precision High-Performance Linpack (HPL) run relative to its immense cost and power draw. Furthermore, the network topologies of AI clusters are heavily optimized for all-reduce operations across massive model-parallel partitions, whereas scientific HPC systems require low-latency, multi-dimensional networks suited for spatial domain decomposition and fast Fourier transforms.

As the ACM SIGHPC takes over the administration of the TOP500 list from the ISC Group, bringing academic digital object identifiers (DOIs) to the rankings, this architectural split will only become more pronounced. LineShine proves that for deep scientific simulation, the CPU is far from dead. By combining modern Armv9 vector extensions with high-bandwidth memory, developers can achieve exascale performance on a highly programmable, general-purpose architecture.